Shen Dong (董珅)

Shen Dong Hello! I am a fourth-year undergraduate student of Computer Science at ACM Class, Shanghai Jiao Tong University. I am currently a research intern at Coordinated Science Laboratory of University of Illinois Urbana-Champaign, having the privilege to be advised by Prof. Yupeng Zhang. I'm also part of Cryptography & System Security Laboratory at Shanghai Jiao Tong University, working with Prof. Yu Yu's group.
I have an extensive interest in Cryptography and I am exploring different fields of Cryptography, especially the area of Post-Quantum Cryptography and Zero-Knowledge Proofs (ZKP). Now I am working on ZKP and its applications, and formerly I have been exploring things on Learning Parity with Noise (LPN). I am also an applicant for the 2025 Fall Ph.D. program in Computer Science.

My CV at here
GitHub: RabbitCabbage
Email: shen-dong@sjtu.edu.cn

Preprints

A Simple Post-Quantum Oblivious Transfer Protocol from Mod-LWR ePrint | Github
S. Dong, H. Cui, K. Zhang, K. Yang, Y. Yu
We construct a simple, efficient OT protocol based on Saber, a Mod-LWR-based key exchange protocol. Our implementation outperforms the state-of-the-art Kyber-based post-quantum OT protocol by Masny and Rindal (CCS’19) in terms of both computation and communication costs.
FAIRZK: A Scalable System to Prove Machine Learning Fairness in Zero-Knowledge
T. Zhang*, S. Dong*, O. Deniz Koze*, Y. Shen, Y. Zhang
We develop efficient zero-knowledge proof protocols for common computations involved in measuring fairness of logistic regression and DNN with tighter bounds.Our experiments demonstrate significant improvements in prover efficiency (speedups ranging from 3.1× to 1789×) and excellent scalability to lagre models (47 million parameters).

Projects

LPN Estimator: I helped to build this tool to estimate the bit security of LPN instances. Input the scale of your instantiations and the noise distribution, and it will give you an estimation of the bit security level based on some known attacks! We mainly considered Information Set Decoding (ISD) and its variant BJMM algorithm. Improvements are still ongoing in our lab.
My Mx Compiler: Given a piece of Java-like language (called Mx), my compiler can compile the code to assembly language. It is implemented in C++. I designed my own Abstract Syntax Tree (AST) and intermediate representation (IR), with some reference to LLVM IR.
My Jigsaw Puzzle CPU: My CPU written in Verilog can run a subset of RISC-V instructions. Implementing Tomasulo Algorithm, my CPU can execute instructions out of order, correctly handling data hazards and control hazards. I even burnt it into a FPGA board and ran successfully! Maybe I can even use it to run the assembly code generated by my compiler...
Train Ticket System: A simulation of China Railway's ticket APP. You can search for appropriate trains, look up time tables, book tickets, and even refund them. Moreover, I co-worked with my classmates to provide a frontend webpage for this system.